1. Field of the Invention
The present invention is directed to automated test equipment (ATE) systems and in particular, to a method, system, and circuitry used to provide digital signal deskew between channels.
2. Background of the Invention
The fundamental operation of an ATE (automatic test equipment) system is to apply stimulus to a device under test (DUT) and capture the response of the DUT to that stimulus. During a digital test, this process consists of applying stimulus vectors—or patterns—to the DUT, waiting for the DUT to produce a stable response to the stimulus, and comparing the response to an expected pattern. Most ATE systems provide a way for the test programmer to control the timing of the response capture with respect to the stimulus. In addition, some ATEs provide the programmer the ability to manually move individual stimulus and response channels with respect to the other channels.
Excessive skew between the various channels of an ATE decreases the maximum pattern (vector) rate of the ATE system. The maximum pattern rate is one factor that can affect device test throughput. The reason the skew between ATE channels has an impact on vector rate can be seen by looking at FIG. 1.
Looking at FIG. 1, the stimulus to the DUT is applied by drivers. Signals arrive at the DUT at different times depending on individual driver speed. Once the signal from the slowest driver arrives, the DUT settling time can begin. The DUT response is captured by receivers in the ATE. Once the slowest receiver has captured the DUT response, the next vector period can begin. The minimum pattern application period (or maximum pattern application rate) is equal to the sum of the driver skew, DUT settling time, and receiver skew. In addition, an ATE system may have other restrictions that increase this minimum period.
The reality and practicality of the situation is that an ATE system may be providing and receiving test patterns and other related signals on thousands of channels connected to a device under test (DUT). Because of physical limitations of the electronic drivers, receivers and signal paths, there is a need to calibrate or deskew the multiple channels on the ATE so that they all are driving at the same moment in time and then also sampling signals from the DUT such that the ATE receives data on channels from the DUT at the same time.
In some cases, in order to test certain aspects of a DUT, it is desirable for a test programmer to intentionally add skew between channels in a controlled fashion. For example, if one ATE channel is supplying a clock to a flip-flop on the DUT and another ATE channel is supplying the data for that flip-flop, the skew between the two channels must be carefully controlled to make sure no setup or hold time specifications are violated. In general, this capability requires very tight control of the skew between ATE channels. Such control of skew cannot be achieved unless the skew of each channel of the ATE has been carefully calibrated to be known or minimal.
During ATE operation, and in order to provide channel-to-channel deskew or controlled skew between channels, most ATE incorporates individual channel or per-pin programmable delay elements. For drive channels, these delay elements are used to move the point in time at which a stimulus is applied to the DUT (hereinafter called the drive edge). For receive channels, similar delay elements control the point in time the DUT response is captured by the ATE (hereinafter the receive edge).
The delay elements used can take many forms, including transmission lines of adjustable length, commercial delay lines (usually consisting of cascaded L/C networks), and chains of logic gates. Any of these implementations will have variations in delay due to temperature, manufacturing process variations, power supply variations, and so forth. Because of these variations, each delay line must be characterized—or calibrated—so that the delays requested by the test programmer can be accurately set by the ATE software. This calibration must typically be repeated when the operating temperature of the system changes.
In the past, one technique used for the calibration of the drive/receive edges and signals was to use a separate instrument, along with the ATE, called a time interval analyzer. A time interval analyzer is basically a device that accurately measures the amount of time that elapses between two signal events. Each channel is routed to the time interval analyzer so that any delay or skew on the channel can be measured with respect to a common reference signal. This technique of calibrating the drive/receive edges of all the channels of an ATE have various disadvantages. One disadvantage is that calibration of the channels must be done in a serial fashion. That is, each channel driver and each channel receiver must be individually measured one after another. Second, a very expensive time interval analyzer is required to achieve the high amount of accuracy desired. Thirdly, the ATE must have a special infrastructure so that each channel (there may be thousands of channels) has a well matched or characterized path to the time interval analyzer so that no additional skew is inadvertently added to any channel.
What is needed is an ATE where the calibration is done for each channel in a parallel manner thereby decreasing calibration time and possible error due to environmental changes (e.g., temperature changes). Furthermore, what is needed is an ATE that does not require an external expensive time interval analyzer instrument to help calibrate the drive and receive edges of the ATE system.